The present invention relates to dual port memories generally and, more particularly, to a dual port memory with a reduced bus latency.
A dual port memory provides two access ports, such as a left port and a right port, that may access a common memory array. Conventional dual port memories may be implemented with 8-T (i.e., 8 transistor) cells in the memory array. FIG. 1 illustrates an example of an 8-T cell 10. The 8-T cell 10 has a first bit-line pair (i.e., RBIT1 and xe2x88x92RBITO) and a second bit-line pair (WR_DATA and xe2x88x92WR_DATA). The bit-line pair RBIT1 and xe2x88x92RBITO is used to read information from the 8-T cell 10 and the bit-line pair WR_DATA and xe2x88x92WR_DATA is used to write information to the 8-T cell 10. Separate bit-line pairs for reading and writing generally require 8 transistors to implement the 8-T cell 10. As densities of memory devices increase, the requirement of duplicating an 8-T cell 10 at each location of the memory array can consume a large amount of die area.
The present invention concerns a dual port memory comprising a memory array, a first address circuit, a second address circuit, a timing circuit, a first data circuit and a second data circuit. The memory array may be configured to (i) write information to a first port or (ii) read information from a second port in response to (i) one or more first timing signals and (ii) one or more second timing signals. The first address circuit may be configured to present one or more first control signals in response to one or more first address signals. The second address circuit may be configured to present one or more second control signals in response to one or more second address signals. The timing circuit may be configured to present the one or more first timing signals and the one or more second timing signals in response to the one or more first control signals and the one or more second control signals. The first data circuit may be configured to read or write information from the first port of the memory array. The second data circuit may be configured to read or write information from the second port of the memory array.
The objects, features and advantages of the present invention include providing a dual port memory that may be (i) implemented with 6-T cell memory locations, (ii) provide access speeds that may be comparable with an 8-T cell dual port memory, (iii) eliminate wait states between consecutive read and write operations and/or (iv) provide an improved throughout by reducing bus latency.